This invention relates to programmable integrated circuit devices, such as programmable logic devices (PLDs), and, more particularly, to configuring such a device as a CIC filter.
As applications for which programmable integrated circuit devices, such as PLDs, are used increase in complexity, it has become more common to design such devices to include specialized processing blocks in addition to blocks of generic programmable logic resources. Such specialized processing blocks may include a concentration of circuitry on a programmable device that has been partly or fully hardwired to perform one or more specific tasks, such as a logical or a mathematical operation. A specialized processing block may also contain one or more specialized structures, such as an array of configurable memory elements. Examples of structures that are commonly implemented in such specialized processing blocks include: multipliers, arithmetic logic units (ALUs), barrel-shifters, various memory elements (such as FIFO/LIFO/SIPO/RAM/ROM/CAM blocks and register files), AND/NAND/OR/NOR arrays, etc., or combinations thereof.
Taking PLDs as one example, one particularly useful type of specialized processing block that has been provided on PLDs is a digital signal processing (DSP) block, which may be used to process, e.g., audio signals. Such blocks are frequently also referred to as multiply-accumulate (“MAC”) blocks, because they include structures to perform multiplication operations, and sums and/or accumulations of multiplication operations.
For example, PLDs sold by Altera Corporation, of San Jose, Calif., as part of the STRATIX® family include DSP blocks, each of which includes four 18-by-18 multipliers. Each of those DSP blocks also includes adders and registers, as well as programmable connectors (e.g., multiplexers) that allow the various components to be configured in different ways. In each such block, the multipliers can be configured not only as four individual 18-by-18 multipliers, but also as four smaller multipliers, or as one larger (36-by-36) multiplier. In addition, one 18-by-18 complex multiplication (which decomposes into two 18-by-18 multiplication operations for each of the real and imaginary parts) can be performed.
Such a DSP block may be configured as a finite impulse response (FIR) filter, with 18-bit data and coefficients. Each block may be used to perform the summation of four 18-by-18 multiplications to form a 4-tap sub-block of a longer FIR filter.
Many types of FIR filters may be encountered. Two of those types are an interpolation FIR filter—in which the number of samples is increased by a factor of n by inserting (“interpolating”) n−1 samples between adjacent samples—and a decimation FIR filter—in which the number of samples is decreased by a factor of n by removing n−1 out of every n samples. A DSP block that may be configured as different types of filters, including an interpolation FIR filter and a decimation FIR filter, is shown in copending, commonly-assigned U.S. patent application Ser. No. 11/447,370, filed Jun. 5, 2006, which is hereby incorporated by reference herein in its entirety.
One particular type of interpolation or decimation filter is the cascaded integrator-comb (“CIC”) filter. A CIC filter can be used as an alternative to a FIR filter, and has the advantage that it can be implemented without multipliers. For high decimation or interpolation factors, the required bit width for full precision may be too large for most practical cases. To reduce the output bit width, quantization is typically applied at the output stage. Based on the nature of decimation filters, Hogenauer developed a pruning strategy to reduce the required bit widths at each stage through truncation or rounding in such a way that the total error introduced will not exceed the quantization error introduced through simple output quantization.
If one were constructing a dedicated CIC filter, there would be a known finite number of stages for which the Hogenauer bit width reductions would have to be calculated. However, in the case of a user-programmable device, the tools provided to the user to program the device must be capable of calculating any number of Hogenauer bit width reductions for any number of CIC filter stages that a user may decide to configure the device as. The calculation of all possible factors could take weeks on the types of computers—i.e., desktop computers—that most programmable device users are likely to use for device configuration.